//////////////////////////////////////////////////////////////////////
////                                                              ////
////  CFBase.v                                                    ////
////                                                              ////
////  This file is part of the core Pico E12 firmware.            ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2005, Pico Computing, INC.                     ////
//// Refer to license.txt for conditions of use.                  ////
//// http://www.picocomputing.com                                 ////
////                                                              ////
////////////////////////////////////////////////////////////////////JF


`include "PicoDefines.v"
`timescale 10ns / 1ps

module CFBase(                                               //----------CF Inputs----------
              CLOCK1_PAD,                                    //50 MHz Free Running Oscillator
              CLOCK2_PAD,                                    //50 MHz Free Running Oscillator for DCM Clock Fix and VCCAuxFix Modules
              CLOCKY9_PAD,
              DCM_KEEPER_PAD,
              CE1_PAD,                                       //CF (Compact Flash) Card Enable 
              CE2_PAD,                                       //CF Card Enable
              REG_PAD,                                       //CF Attribute Memory Transfer
              IORD_PAD,                                      //CF IO Space Read from Card
              IOWR_PAD,                                      //CF IO Space Write to Card
              OE_PAD,                                        //CF Memory Space Read from Card
              WE_PAD,                                        //CF Memory Space Write to Card

                                                             //----------CF Outputs---------
              READY_PAD,                                     //CF Interrupt Request
              WAIT_PAD,                                      //CF Extend Data Transfer Request
              WP_IOIS16_PAD,                                 //CF WriteProtect (Memory) / 16 Bit IO
              INPACK_PAD,                                    //CF IO Transfer Acknowledge
              BVD1_PAD,                                      //CF Battery Voltage Detect #1
              BVD2_PAD,                                      //CF Battery Voltage Detect #2

                                                             //-------CF Control Lines------
              MASTEREN_PAD,                                  //CF Master Transeciver Power Enable
              ADDRESSDIR_PAD,                                //CF Input Transeivers Direction Select
              CTRLDIR_PAD,                                   //CF Output Transeivers Direction Select
              DATADIRH_PAD,                                  //CF D0 - D7 Transceiver Direction Select
              DATADIRL_PAD,                                  //CF D8 - D15 Transceiver Driection Select
              
                                                             //-----CF Data/Address Bus-----
              D_PAD0,                                        //CF Bidirectional Databus
              D_PAD1,
              D_PAD2,
              D_PAD3,
              D_PAD4,
              D_PAD5,
              D_PAD6,
              D_PAD7,
              D_PAD8,
              D_PAD9,
              D_PAD10,
              D_PAD11,
              D_PAD12,
              D_PAD13,
              D_PAD14,
              D_PAD15,

              A_PAD0,                                        //CF Address bus
              A_PAD1,
              A_PAD2,
              A_PAD3,
              A_PAD4,
              A_PAD5,
              A_PAD6,
              A_PAD7,
              A_PAD8,
              A_PAD9,
              A_PAD10,

              FLASH_CE_PAD,                                  //Flash Control Signals
              FLASH_OE_PAD,
              FLASH_WE_PAD,
              FLASH_WP_PAD,
              FLASH_RESET_PAD,
              FLASH_BYTE_PAD,

              FLASH_BUSY_PAD,                                //Flash Status Signal
                  
              FLASHD_PAD0,                                   //Flash DataBus                                       
              FLASHD_PAD1,
              FLASHD_PAD2,
              FLASHD_PAD3,
              FLASHD_PAD4,
              FLASHD_PAD5,
              FLASHD_PAD6,
              FLASHD_PAD7,
              FLASHD_PAD8,
              FLASHD_PAD9,
              FLASHD_PAD10,
              FLASHD_PAD11,
              FLASHD_PAD12,
              FLASHD_PAD13,
              FLASHD_PAD14,
              FLASHD_PAD15,

              FLASHA_PAD0,                                 //Flash AddressBus
              FLASHA_PAD1,
              FLASHA_PAD2,
              FLASHA_PAD3,
              FLASHA_PAD4,
              FLASHA_PAD5,
              FLASHA_PAD6,
              FLASHA_PAD7,
              FLASHA_PAD8,
              FLASHA_PAD9,
              FLASHA_PAD10,                                     
              FLASHA_PAD11,
              FLASHA_PAD12,
              FLASHA_PAD13,
              FLASHA_PAD14,
              FLASHA_PAD15,
              FLASHA_PAD16,
              FLASHA_PAD17,
              FLASHA_PAD18,
              FLASHA_PAD19, 
              FLASHA_PAD20,                                       
              FLASHA_PAD21,
              FLASHA_PAD22,
              FLASHA_PAD23,
              FLASHA_PAD24,
              FLASHA_PAD25,
                  
              CPLD_PEEKABOO_PAD,
              CPLD_RELOAD_PAD,

              JTAG_LOOPBACK_TCK_PAD,
              JTAG_LOOPBACK_TDI_PAD,
              JTAG_LOOPBACK_TDO_PAD,
              JTAG_LOOPBACK_TMS_PAD

`ifdef ENABLE_GPIO_PADS     //JBC - 2/22/07 - this ifdef was originally tied to ENABLE_GPIO, but we
             ,GPIO_PAD1,    // do not want ENABLE_GPIO for RS-232 but we need these pads enabled
              GPIO_PAD2,
              GPIO_PAD3,
              GPIO_PAD4
`endif


`ifdef ENABLE_ETH
  ,ETHER_GTX_CLK,
   ETHER_RX_CLK,
   ETHER_RX_CTL,
   ETHER_RX_ER,
   ETHER_RX,
   ETHER_TX_CLK,
   ETHER_TX_EN,
   ETHER_TX_ER,
   ETHER_TX
`endif //ENABLE_ETH

`ifdef ENABLE_MDIO_LOW_LEVEL
    ,ETHER_25MHZ_PAD,
   ETHER_COMA_PAD, 
   ETHER_MDC_PAD,
   ETHER_MDIO_PAD, 
   ETHER_RESET_PAD
`endif //ENABLE_MDIO_LOW_LEVEL

`ifdef ENABLE_RAM_PADS
             ,RAM_D_PAD0,
              RAM_D_PAD1,
              RAM_D_PAD2,
              RAM_D_PAD3,
              RAM_D_PAD4,
              RAM_D_PAD5,
              RAM_D_PAD6,
              RAM_D_PAD7,
              RAM_D_PAD8,
              RAM_D_PAD9,
              RAM_D_PAD10,
              RAM_D_PAD11,
              RAM_D_PAD12,
              RAM_D_PAD13,
              RAM_D_PAD14,
              RAM_D_PAD15,
              RAM_D_PAD16,
              RAM_D_PAD17,
              RAM_D_PAD18,
              RAM_D_PAD19,
              RAM_D_PAD20,
              RAM_D_PAD21,
              RAM_D_PAD22,
              RAM_D_PAD23,
              RAM_D_PAD24,
              RAM_D_PAD25,
              RAM_D_PAD26,
              RAM_D_PAD27,
              RAM_D_PAD28,
              RAM_D_PAD29,
              RAM_D_PAD30,
              RAM_D_PAD31,

              RAM_A_PAD0,
              RAM_A_PAD1,
              RAM_A_PAD2,
              RAM_A_PAD3,
              RAM_A_PAD4,
              RAM_A_PAD5,
              RAM_A_PAD6,
              RAM_A_PAD7,
              RAM_A_PAD8,
              RAM_A_PAD9,
              RAM_A_PAD10,
              RAM_A_PAD11,
              RAM_A_PAD12,

              RAM_DM_PAD0,
              RAM_DM_PAD1,
              RAM_DM_PAD2,
              RAM_DM_PAD3,

              RAM_BA_PAD0,
              RAM_BA_PAD1,
              
              RAM_WE_PAD,
              RAM_CLKE_PAD,
              RAM_CS_PAD,
              RAM_CAS_PAD,
              RAM_RAS_PAD,
              RAM_CLK_PAD
           `endif // ENABLE_RAM_PADS   
);

//-----------------------------------Signals for the Compact Flash Decoders---------------------------------//                 
wire              CLOCK1;
wire              CLOCK2;
wire              CLOCKY9;      //JBC - 2/27/07 - added wire for CLOCKY9, there was no wire
wire              DCM_KEEPER;
wire              CE1;
wire              CE2;
wire              REG;
wire              IORD;
wire              IOWR; 
wire              OE;
wire              WE;                                    
wire              READY;
wire              WAIT;    
wire              WP_IOIS16;
wire              INPACK; 
wire              BVD1;   
wire              BVD2;                            
wire              MASTEREN; 
wire              ADDRESSDIR;
wire              CTRLDIR; 
wire              DATADIRH; 
wire              DATADIRL;
wire              DATATRISH;
wire              DATATRISL;
wire              CF_ADDRESSDIR;
wire              CF_CTRLDIR; 
wire              CF_DATADIRH; 
wire              CF_DATADIRL;
wire              CF_DATATRISH;
wire              CF_DATATRISL;

wire              [15:0]DIN;
wire              [15:0]DOUT;
wire              [10:0]A;

//------------------------------------------Main Signals for the User-----------------------------------------//
wire              CFClock;          
wire              [15:0]DataIn;
wire              [15:0]DataOut;
wire              [15:0]MemDataOut;
wire              [15:0]IODataOut;                                                                                
wire              [31:0]MemAddress;
wire              [`PCMCIA_ADR_LINES-1:0]IOAddress;
wire              MemRead;
wire              MemWrite;
wire              AttribRead;
wire              AttribWrite;
wire              IORead;
wire              IOWrite;
wire              ByteMode;

//------------------------------------------Signals for the Peripherals---------------------------------------//
wire              FLASH_TRIS_D;
wire              FLASH_TRIS_D15;
wire              FLASH_TRIS_A;
wire              [15:0]FLASH_DIN;
wire              [15:0]FLASH_DOUT;
wire              [25:0]FLASH_AIN;
wire              [25:0]FLASH_AOUT;
wire              FLASH_AOUT_NEG_ONE;
wire              FLASH_CE;
wire              FLASH_OE;
wire              FLASH_WE;
wire              FLASH_WP;
wire              FLASH_RESET;
wire              FLASH_BYTE;
wire              FLASH_BUSY;

wire              CPLD_PEEKABOO;     //hrgt: for standalone Jun 6, 2007
wire              CPLD_RELOAD;       //hrgt: for standalone Jun 6, 2007
wire              CPLD_PEEKABOO_PPC; //hrgt: for standalone Jun 6, 2007
wire              CPLD_RELOAD_PPC;   //hrgt: for standalone Jun 6, 2007
wire              CPLD_PEEKABOO_CF;  //hrgt: for standalone Jun 6, 2007
wire              CPLD_RELOAD_CF;    //hrgt: for standalone Jun 6, 2007
assign CPLD_PEEKABOO = CPLD_PEEKABOO_CF | CPLD_PEEKABOO_PPC;
assign CPLD_RELOAD   = CPLD_RELOAD_CF   | CPLD_RELOAD_PPC;

wire              JTAG_LOOPBACK_TCK;
wire              JTAG_LOOPBACK_TDI;
wire              JTAG_LOOPBACK_TDO;
wire              JTAG_LOOPBACK_TMS;


`ifdef ENABLE_GPIO_PADS                 //JBC - 2/22/07 - this ifdef was originally tied to ENABLE_GPIO, but we
   wire           [4:1]GPIO_IN;         // do not want ENABLE_GPIO for RS-232 but we need these pads enabled
   wire           [4:1]GPIO_OUT;
   wire           [4:1]GPIO_TRIS;
`endif

`ifdef ENABLE_RAM_PADS
   wire [0:31] RAM_D_I, RAM_D_O, RAM_D_T;
   wire [12:0] RAM_A;
   wire [0:3] RAM_DM;
   wire RAM_WE;
   wire RAM_CLKE;
   wire RAM_CS;
   wire RAM_CAS;
   wire RAM_RAS;
   wire RAM_CLK;
   wire [0:1] RAM_BA;
`endif // ENABLE_RAM_PADS

`ifdef ENABLE_CPU
   wire        OPB_Clk;
   wire        OPB_Clk90;
   wire        OPB_Rst;
   wire [31:0] OPB_ABus;
   wire [3:0]  OPB_BE;
   wire [31:0] OPB_DBus;
   wire        OPB_RNW;
   wire        OPB_select;
   wire        OPB_seqAddr;
   wire [31:0] Sl_DBus_ext;
   wire        Sl_errAck_ext;
   wire        Sl_retry_ext;
   wire        Sl_toutSup_ext;
   wire        Sl_xferAck_ext;
`endif //ENABLE_CPU

//--------------------------------------------------Other Signals---------------------------------------------//
wire              MemWait;
wire              BackplaneDetected;
wire              DetectorBusy;

// This goes directly from the PPCSystem module to the CF output data bus.
wire [15:0] CPUCFDataOut;

//We'll swap control of the memory peripheral bus between the on-chip cpu and the cf bus
wire         CPUMemMaster;
wire [31:0]  CPUMemAddress, CFMemAddress;
wire [15:0]  CPUDataIn, CFDataIn;
wire         CPUMemRead, CPUMemWrite, CPUAttribRead, CPUAttribWrite, CPUIORead, CPUIOWrite;
wire         CFMemRead,  CFMemWrite,  CFAttribRead,  CFAttribWrite,  CFIORead,  CFIOWrite;
wire         PPCDcmsLocked;
wire [127:0] PPCTestPins;

`ifndef ENABLE_PPC
   // This will cause all the muxes below to be optimized away.
   assign CPUMemMaster  = 0;
   assign CPUDataOut    = 16'h0;
   assign CPUCFDataOut  = 16'h0;
   assign PPCDcmsLocked = 1'b1;
   assign CPUMemRead = 0;
   assign CPUMemWrite = 0;
   assign CPUMemAddress = 31'h0;
`endif

assign MemAddress  = CPUMemMaster ? CPUMemAddress  : CFMemAddress;
assign DataIn      = CPUMemMaster ? CPUDataIn      : CFDataIn;
assign MemRead     = CPUMemMaster ? CPUMemRead     : CFMemRead;
assign MemWrite    = CPUMemMaster ? CPUMemWrite    : CFMemWrite;
assign AttribRead  = CPUMemMaster ? CPUAttribRead  : CFAttribRead;
assign AttribWrite = CPUMemMaster ? CPUAttribWrite : CFAttribWrite;
assign IORead      = CPUMemMaster ? CPUIORead      : CFIORead;
assign IOWrite     = CPUMemMaster ? CPUIOWrite     : CFIOWrite;

//---------------------------------Low Level Locaton Constraints and Primitives-------------------------------//
//                                                                                                            //
//The following include files do the following:                                                              //
//      -Declare input and output pins                                                                       //
//      -Set the location and IO standard of all the pins in this design                                     //
//      -Instantiate IO buffers                                                                              //
`include "..\src\CFBaseLowLevel.v"
`ifdef ENABLE_RAM_PADS
   `include "..\src\RamLowLevel.v"
`endif

//---------------------------------------------ChipScope Debug Taps-------------------------------------------//
//                                                                                                            //
//The following include file does the following:                                                              //
//      -Instantiates Taps for all Compact Flash user signals                                                 //
//      -Instantiates Taps for the Compact Flash databus
`ifdef ENABLE_DEBUG_TAPS
    `include "..\src\CFBaseChipScopeTaps.v"
`endif

//--------------------------------------------- Backplane detection ------------------------------------------//
//                                                                                                            //
//This code determines if a Backplane is present
  BackplaneDetector #(16)                                                                                     //JF - See me before adjusting
  BackplaneDetector(.CLOCK1(CLOCK1), .DETECTOR(READY_OUT), .DetectorBusy(DetectorBusy),
                                     .MASTEREN(MASTEREN),  .BackplaneDetected(BackplaneDetected));

assign ADDRESSDIR = (DetectorBusy) ? 0 : CF_ADDRESSDIR;         
assign CTRLDIR    = (DetectorBusy) ? 0 : CF_CTRLDIR;               
assign DATADIRH   = (DetectorBusy) ? 0 : CF_DATADIRH;             
assign DATADIRL   = (DetectorBusy) ? 0 : CF_DATADIRL;             
assign DATATRISL  = (DetectorBusy) ? 1 : CF_DATATRISL;          
assign DATATRISH  = (DetectorBusy) ? 1 : CF_DATATRISH;          

//---------------------------------------------Compact Flash Decoder------------------------------------------//
//                                                                                                            //
//The CF Decoder does the following:                                                                          //
//      -Decodes the raw Compact Flash databus                                                                //
//      -Impliments a Tuple                                                                                   //
//      -Impliments address extension and mandatory CF registers                                              //

CFDecoder CFDecoder(
                .CLOCK1(CLOCK1),
                .CLOCK2(CLOCK2),
                .CFClock(CFClock),
                .DCM_KEEPER(DCM_KEEPER),
                .CE1_DIRTY(CE1),
                .CE2_DIRTY(CE2),
                .REG(REG),
                .IORD(IORD),
                .IOWR(IOWR), 
                .OE(OE),
                .WE(WE),                                    
                .READY(READY),    
                .WP_IOIS16(WP_IOIS16),
                .INPACK(INPACK), 
                .BVD1(BVD1),   
                .BVD2(BVD2),                                 
                .CF_ADDRESSDIR(CF_ADDRESSDIR),
                .CF_CTRLDIR(CF_CTRLDIR), 
                .CF_DATADIRH(CF_DATADIRH), 
                .CF_DATADIRL(CF_DATADIRL),
                     .CF_DATATRISH(CF_DATATRISH),
                     .CF_DATATRISL(CF_DATATRISL),
                .DIN(DIN[15:0]),
                .DOUT(DOUT[15:0]),
                .A(A[10:0]),

                .DataIn(CFDataIn[15:0]),
                .DataOut(DataOut[15:0]),
                .MemAddress(CFMemAddress[31:0]),
                .IOAddress(IOAddress[`PCMCIA_ADR_LINES-1:0]),
                .MemRead(CFMemRead),
                .MemWrite(CFMemWrite),
                .AttribRead(CFAttribRead),
                .AttribWrite(CFAttribWrite),
                .IORead(CFIORead),
                .IOWrite(CFIOWrite),
                .ByteMode(ByteMode)
); //CFDecoder

//Combine some signals between the main peripheral busses
assign DataOut[15:0] = (MemDataOut[15:0] | IODataOut[15:0] | CPUCFDataOut[15:0]);
assign WAIT = ~MemWait;

//----------------------------Peripherals in common and configuration memory----------------------------------//
//                                                                                                            //
//This is the module that attaches to all the peripherals located in common and configuration memory          //
// 
MemoryPeripherals MemoryPeripherals(
   .CLOCK1(CLOCK1),
   .CLOCK2(CLOCK2),
   .CLOCKY9(CLOCKY9),
   .AttribRead(AttribRead),
   .AttribWrite(AttribWrite),
   .MemRead(MemRead), 
   .MemWrite(MemWrite), 
   .MemAddress(MemAddress[31:0]), 
   .DataIn(DataIn[15:0]), 
   .DataOut(MemDataOut[15:0]), 
   .ByteMode(ByteMode), 
   .Wait(MemWait),

   .FLASH_CE(FLASH_CE), 
   .FLASH_OE(FLASH_OE), 
   .FLASH_WE(FLASH_WE), 
   .FLASH_WP(FLASH_WP), 
   .FLASH_BYTE(FLASH_BYTE), 
   .FLASH_AIN(FLASH_AIN[25:0]), 
   .FLASH_AOUT(FLASH_AOUT[25:0]),
   .FLASH_AOUT_NEG_ONE(FLASH_AOUT_NEG_ONE),
   .FLASH_DIN(FLASH_DIN[15:0]),
   .FLASH_DOUT(FLASH_DOUT[15:0]),
   .FLASH_TRIS_D(FLASH_TRIS_D),
   .FLASH_TRIS_D15(FLASH_TRIS_D15),
   .FLASH_TRIS_A(FLASH_TRIS_A),
   .CPLD_RELOAD_CF(CPLD_RELOAD_CF),       //hrgt Jun 6, 2007 for standalone 
   .CPLD_PEEKABOO_CF(CPLD_PEEKABOO_CF),   //JBC, hrgt Jun 6, 2007 for standalone
   .CPLD_RELOAD_PPC(CPLD_RELOAD_PPC),     //hrgt Jun 6, 2007 for standalone 
   .CPLD_PEEKABOO_PPC(CPLD_PEEKABOO_PPC), //JBC, hrgt Jun 6, 2007 for standalone

	//added for RapidHDL
	`ifdef ENABLE_RAM_PADS
		.RamAddr(RAM_A),
		.RamDM(RAM_DM),
		.RamWE(RAM_WE),
		.RamClkE(RAM_CLKE),
		.RamCS(RAM_CS),
		.RamCAS(RAM_CAS),
		.RamRAS(RAM_RAS),
		.RamClk(RAM_CLK),
		.RamBA(RAM_BA),
		.RamDOut(RAM_D_O),
		.RamDIn(RAM_D_I),
		.RamDT(RAM_D_T),
	`endif // ENABLE_RAM_PADS 
	
	
   `ifdef ENABLE_GPIO                   
      .GPIO_IN(GPIO_IN[4:1]),       
      .GPIO_OUT(GPIO_OUT[4:1]),
      .GPIO_TRIS(GPIO_TRIS[4:1]),  //JBC
   `endif
   
   `ifdef ENABLE_MDIO
      .MDIO_IN(ETHER_MDIO_I),
        .MDIO_OUT(ETHER_MDIO_O),
        .MDC(ETHER_MDC),
        .TRIS_MDIO(ETHER_MDIO_T),
      .ETH_25MHZ(ETHER_25MHZ), 
      .ETH_COMA(ETHER_COMA),
      .ETH_RESET(ETHER_RESET),
   `endif
   
   
   //OPB
`ifdef ENABLE_PPC //JBC - we do not want these signals if we are building the LX part
   .OPB_Clk(OPB_Clk),
   .OPB_Clk90(OPB_Clk90),
   .OPB_Rst(OPB_Rst),
   .OPB_ABus(OPB_ABus),
   .OPB_BE(OPB_BE),
   .OPB_DBus(OPB_DBus),
   .OPB_RNW(OPB_RNW),
   .OPB_select(OPB_select),
   .OPB_seqAddr(OPB_seqAddr),
   .Sl_DBus_ext(Sl_DBus_ext [31:0]),
   .Sl_errAck_ext(Sl_errAck_ext),
   .Sl_retry_ext(Sl_retry_ext),
   .Sl_toutSup_ext(Sl_toutSup_ext),
   .Sl_xferAck_ext(Sl_xferAck_ext),
`endif // ENABLE_PPC

   .CFClock(CFClock)
);

//----------------------------------Peripherals in the IO address space---------------------------------------//
//                                                                                                            //
// 


IOPeripherals IOPeripherals(.IORead(IORead),
                            .IOWrite(IOWrite),
                            .IOAddress(IOAddress[`PCMCIA_ADR_LINES-1:0]),
                            .DataIn(DataIn[15:0]),
                            .DataOut(IODataOut[15:0]),
                            .JTAG_LOOPBACK_TCK(JTAG_LOOPBACK_TCK), 
                            .JTAG_LOOPBACK_TDI(JTAG_LOOPBACK_TDI),
                            .JTAG_LOOPBACK_TDO(JTAG_LOOPBACK_TDO), 
                            .JTAG_LOOPBACK_TMS(JTAG_LOOPBACK_TMS),
                            .FLASH_RESET(FLASH_RESET),
                            .FLASH_BUSY(FLASH_BUSY),
                            .DcmsLocked(PPCDcmsLocked),
                            .BackplaneDetected(BackplaneDetected));


//----------------------------CPU system----------------------------------------------------------------------//
//                                                                                                            //
//The CPU system and its buses and other paraphernalia are quarantined within                                 //
//This usually comes from a netlist (blackbox) built by EDK                                                   //
//
`ifdef ENABLE_PPC
PPCSystem PPCSystem(
   .Clk(CLOCKY9),
   .Clk200(CFClock),
   .Rst(1'b0),
   .StandaloneSw(BackplaneDetected),

   .FLASH_AIN(FLASH_AIN[25:0]), //JBC June 8, 2007

   .CPUMemMaster(CPUMemMaster),
   .MemReadMaster(CPUMemRead),
   .MemWriteMaster(CPUMemWrite),
   .MemWait(MemWait),
   .AttrReadMaster(CPUAttribRead),   //hrgt: 5/27/2007 corrected spelling
   .AttrWriteMaster(CPUAttribWrite), //hrgt: 5/27/2007 corrected spelling
   .IOReadMaster(CPUIORead),
   .IOWriteMaster(CPUIOWrite),
   .MemAddrMaster(CPUMemAddress[31:0]),

   .CPLD_PEEKABOO_PPC(CPLD_PEEKABOO_PPC),
   .CPLD_RELOAD_PPC(CPLD_RELOAD_PPC),
                   
   .IOAddr(IOAddress),
   .IORead(IORead),
   .IOWrite(IOWrite),
   .CFIORead(CFIORead),   
   .CFIOWrite(CFIOWrite),
   .DataIn(CPUDataIn[15:0]),
   .DataOut(MemDataOut[15:0]),
   .CFDataIn(CFDataIn[15:0]),        //DRP: 1/10/07 corrected keyhole versus CPUMemMaster problem
   .CFDataOut(CPUCFDataOut[15:0]),   //DRP: 1/10/07 corrected keyhole versus CPUMemMaster problem
   .RamAddr(RAM_A),
   .RamDIn(RAM_D_I),
   .RamDOut(RAM_D_O),
   .RamDT(RAM_D_T),
   .RamDM(RAM_DM),
   .RamWE(RAM_WE),
   .RamClkE(RAM_CLKE),
   .RamCS(RAM_CS),
   .RamCAS(RAM_CAS),
   .RamRAS(RAM_RAS),
   .RamClk(RAM_CLK),
   .RamBA(RAM_BA),
   .DcmsLocked(PPCDcmsLocked),

   //OPB
   .OPB_Clk(OPB_Clk),
   .OPB_Clk90(OPB_Clk90),
   .OPB_Rst(OPB_Rst),
   .OPB_ABus(OPB_ABus),
   .OPB_BE(OPB_BE),
   .OPB_DBus(OPB_DBus),
   .OPB_RNW(OPB_RNW),
   .OPB_select(OPB_select),
   .OPB_seqAddr(OPB_seqAddr),
   .Sl_DBus_ext(Sl_DBus_ext [31:0]),
   .Sl_errAck_ext(Sl_errAck_ext),
   .Sl_retry_ext(Sl_retry_ext),
   .Sl_toutSup_ext(Sl_toutSup_ext),
   .Sl_xferAck_ext(Sl_xferAck_ext)
   
   `ifdef ENABLE_GPIO_PADS              //JBC - 2/22/07 - the GPIO pins were not being passed to PPC system
      ,.GPIO_IN(GPIO_IN[4:1]),              // we need these pins for RS-232 to work
      .GPIO_OUT(GPIO_OUT[4:1]),
      .GPIO_TRIS(GPIO_TRIS[4:1])
   `endif
   
   `ifdef ENABLE_ETH //{
      ,.ETHER_GTX_CLK  (ETHER_GTX_CLK),
      //   .ETHER_25MHZ   (ETHER_25MHZ), 
      .ETHER_COMA    (ETHER_COMA),  
      .ETHER_MDC     (ETHER_MDC),   
      .ETHER_MDIO_I  (ETHER_MDIO_I),  
      .ETHER_MDIO_O  (ETHER_MDIO_O),  
      .ETHER_MDIO_T  (ETHER_MDIO_T),  
      .ETHER_RESET   (ETHER_RESET), 
      .ETHER_RX_CLK  (ETHER_RX_CLK),
      .ETHER_RX_CTL  (ETHER_RX_CTL),
      .ETHER_RX_ER   (ETHER_RX_ER), 
      .ETHER_RX      (ETHER_RX),    
      .ETHER_TX_CLK  (ETHER_TX_CLK),
      .ETHER_TX_EN   (ETHER_TX_EN),
      .ETHER_TX_ER   (ETHER_TX_ER), 
      .ETHER_TX      (ETHER_TX)    
   `endif //ENABLE_ETH }
   
   //,.test_pins(PPCTestPins)
);
`endif // ENABLE_PPC


//Following link various signals into DebugTap structure for Chipscope.
`ifdef _DEBUG
wire [100:0] keeper;
//synthesis attribute KEEP of keeper is TRUE;
//{
DebugTap               CPUMemMaster_tap   (CPUMemMaster,        keeper[ 0]); 
DebugTap #(.Width(32)) CPUMemAddress_tap  (CPUMemAddress[31:0], keeper[ 1]); 
DebugTap #(.Width(16)) CPUDataIn_tap      (CPUDataIn[15:0],     keeper[ 2]); 
DebugTap #(.Width(32)) CFMemAddress_tap   (CFMemAddress[31:0],  keeper[ 3]); 
DebugTap #(.Width(16)) CFDataIn_tap       (CFDataIn[15:0],      keeper[ 4]); 
DebugTap               CPUMemRead_tap     (CPUMemRead,          keeper[ 5]); 
DebugTap               CPUMemWrite_tap    (CPUMemWrite,         keeper[ 6]);
DebugTap               CPUAttribRead_tap  (CPUAttribRead,       keeper[ 7]);
DebugTap               CPUAttribWrite_tap (CPUAttribWrite,      keeper[ 8]);
DebugTap               CPUIORead_tap      (CPUIORead,           keeper[ 9]);
DebugTap               CPUIOWrite_tap     (CPUIOWrite,          keeper[10]); 
DebugTap               CFMemRead_tap      (CFMemRead,           keeper[11]);
DebugTap               CFMemWrite_tap     (CFMemWrite,          keeper[12]);
DebugTap               CFAttribRead_tap   (CFAttribRead,        keeper[13]);
DebugTap               CFAttribWrite_tap  (CFAttribWrite,       keeper[14]);
DebugTap               CFIORead_tap       (CFIORead,            keeper[15]);
DebugTap               CFIOWrite_tap      (CFIOWrite,           keeper[16]);
DebugTap #(.Width(16)) CPUCFDataOut_tap   (CPUCFDataOut[15:0],  keeper[17]);
//}
`endif

endmodule
